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Why do CPUs have multiple cache levels?
This is a reader question from “jlforrest” that seems worth answering in more detail than just a single sentence: I understand the need for a cache but I don’t understand why there are …
Fabian Giesen
When I grow up I'll be an inventor.
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2
Memory bandwidth
Absolute memory bandwidth figures tend to look fairly large, especially for GPUs. This is deceptive. It’s much more useful to relate memory bandwidth to say the number of clock cycles or inst…
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How many x86 instructions are there?
It’s surprisingly hard to give a good answer (the question was raised in this article). It depends on how you count, and the details are interesting (to me anyway). To not leave you hanging: …
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SSE: mind the gap
SSE and SSE2 are available in every single x86-family CPU with 64-bit support. You too can play around with SIMD, which is great fun! Unfortunately, SSE2 level in particular also happens to be what…