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Why do CPUs have multiple cache levels?
This is a reader question from “jlforrest” that seems worth answering in more detail than just a single sentence: I understand the need for a cache but I don’t understand why there are …
Fabian Giesen
When I grow up I'll be an inventor.
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Visit fgiesen.wordpress.com → RSS feedOn Hacker News Aug 2011 – Oct 2026
Systems & Performance 10Math & Algorithms 8Software Engineering 7Hardware & Electronics 4Games & Graphics 2Networking & Internet 1
2
Papers I like
This started out on Twitter and I expected having to write up maybe 50 or so, but then it made the rounds. I don’t think I have 1200+ papers that I’d recommend reading, and even if I di…
3
On AlphaTensor’s new matrix multiplication algorithms
Two acquaintances independently asked about this today, so it seems worth a write-up: recently (as of this writing), DeepMind published a new paper about a new practical fast matrix multiplication …
4
Memory bandwidth
Absolute memory bandwidth figures tend to look fairly large, especially for GPUs. This is deceptive. It’s much more useful to relate memory bandwidth to say the number of clock cycles or inst…
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How many x86 instructions are there?
It’s surprisingly hard to give a good answer (the question was raised in this article). It depends on how you count, and the details are interesting (to me anyway). To not leave you hanging: …
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A trip through the Graphics Pipeline
Welcome. This is the index page for a series of blog posts I’m currently writing about the D3D/OpenGL graphics pipelines as actually implemented by GPUs. A lot of this is well known among gra…
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Reading and writing are less symmetric than you (probably) think
I am talking about the I/O operations as used in computing here. A typical example of how this kind of thing is exposed are the POSIX syscalls read(2) and write(2), which have the following C funct…
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Metaprogramming for madmen
This post is part of the series “Debris: Opening the box”. Okay, previous posts from this series aimed to actually convey useful technical information: assuming you actually want to wri…
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Network Latencies and Speed of Light
In this short post I’m going to attempt to convince you that current network (Internet) latencies are here to stay, because they are already within a fairly small factor of what is possible u…
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Low-level x86 code compression for 64k intros
This is about the “secret ingredient” in my EXE packer kkrunchy, which was used in our (Farbrausch) 64k intros starting from “fr-030: Candytron”, and also in a lot of other …
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Zero or Sign Extend
A while back I had to deal with a bit-packed format that contained a list of integer values encoded in one of a pre-defined sets of bit widths, where both the allowed bit widths and the signed-ness…
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SSE: mind the gap
SSE and SSE2 are available in every single x86-family CPU with 64-bit support. You too can play around with SIMD, which is great fun! Unfortunately, SSE2 level in particular also happens to be what…
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Reading bits in far too many ways
Resurrecting an old tradition of this blog, let’s take a simple problem, go over a way too long list of alternative solutions, and evaluate their merits. Our simple problem is this: we want t…
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Quaternion Differentiation (2012)
I wanted to point someone to a short explanation of this today and noticed, with some surprise, that I couldn’t find something concise within 5 minutes of googling. So it seems worth writing …
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Cache tables
Hash tables are the most popular probabilistic data structure, by quite a margin. You compute some hash code then compute an array index from that hash code. If you’re using open addressing-c…
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A whirlwind introduction to dataflow graphs
While in the middle of writing “Reading bits in far too many ways, part 3”, I realized that I had written a lot of background material that had absolutely nothing to do with bit I/O and…
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Papers I like (part 2)
Continued from part 1. Once I was about a thousand words into describing background for GEMM, it became pretty clear that it made more sense to group the numerical math papers into one post, so her…