Samsung Semiconductor Tech Blog company blog

Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm

Samsung Electronics' Semiconductor Research Center presented the paper “First Demonstration of 3D Stacked FETs at Gate Pitch of 42 nm Featuring Triple Stacked Nanosheet Channels for Advanced Logic Applications” at the 2026 VLSI Symposium, held from June 14–18.
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Hardware & ElectronicsScience & Space2026

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Jun 19, 2026Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm by its_ajseven12746

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