Georg's Log personal blog
Programming with RISC-V Vector Instructions
Perhaps the most interesting part of the open RISC-V instruction set architecture (ISA) is the vector extension (RISC-V "V"). In contrast to the average single-instruction multipe-data (SIMD) instruction set, RISC-V vector instructions are vector length agnostic (VLA). Thus, a RISC-V "V" CPU is flexible in choosing a…
- Points
- 162
- HN comments
- 35
- Submissions
- 1
- Cited by
- 6 commenters
Software EngineeringHardware & Electronics2020
On Hacker News
| Submitted | Title on HN | Points | Comments |
|---|---|---|---|
| Aug 6, 2020 | Programming with RISC-V Vector Instructions by pantalaimon | 162 | 35 |
Cited in comments
Linked from 6 Hacker News comments by 6 different people, from Aug 2020 to Jun 2023.
Most recent:
- photochemsyn · Jun 1, 2023
- ZeroCool2u · Mar 6, 2023
- jakeogh · Feb 8, 2022
- twic · Aug 17, 2021
- monocasa · Sep 5, 2020
- pantalaimon · Aug 6, 2020
