A site made for SoC Architects, RTL Designers, DV, Emulation and Validation Engineers, that condenses decades of SoC/ASIC development experience into easy to understand tutorials with tons of code examples
Visit systemverilog.io → On Hacker News Nov 2019 – Mar 2026
A detailed tutorial on DDR4 SDRAM Initialization, Training and Calibration. Exploring topics such as Read/Write Training, ZQ Calibration, Vref Training, Read Centering, Write Centering, Write Leveling and Periodic Calibration.
A detailed tutorial on DDR4 SDRAM Initialization, Training and Calibration. Exploring topics such as Read/Write Training, ZQ Calibration, Vref Training, Read Centering, Write Centering, Write Leveling and Periodic Calibration.