Divyansh Agrawal

Research notes and experiments on machine learning systems, reinforcement learning, evaluations, and language models.

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Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5

2026705 points147 comments Hardware & Electronics details

I compiled a RISC-V CPU into Qwen 3.5 4B's weights, using its Gated DeltaNet layers as RAM. It runs C and MicroPython inside the forward passes, and Qwen uses it for exact arithmetic.